Wafers used in semiconductor fabrication are typically formed from a crystalline material, such as bulk silicon. In particular, very specific types of single crystals of silicon, known as boules, are grown into long lengths and thin slices (e.g., wafers) are cut there-from. The crystalline structure of the wafers is advantageous in forming semiconductor devices because it facilitates control over the electrical properties of the devices and exhibits uniform electrical performance throughout the entire semiconductor material. Additionally, because impurities that degrade device performance tend to collect around irregularities in the atomic structure of a material, the regularity of the crystalline structure provides for very predictable device performance and yield.
In forming semiconductor devices on silicon wafers, the wafers generally go through many fabrication stages. Consequently, the wafers may pass through different semiconductor processing tools one or more times. One such tool is an ion implanter. Ion implanters are utilized to selectively bombard regions of a wafer with ions of a dopant material. The ions penetrate into the wafer and alter the composition thereof, thus giving the regions of the wafer particular electrical characteristics, such a may be useful for fashioning certain semiconductor devices, such as transistors, upon the wafer.
It can be appreciated that the orientation of a wafer relative to a processing tool can be important. With regard to ion implanters, for example, it may be desirable to “align” the wafer with a beam of dopant ions so that few ions encounter the lattice structure of the wafer and the ions are thereby implanted relatively deeply into the wafer or substrate. Alternatively, it may be desirable to somewhat “mis-align” the wafer so that some of the ions encounter the lattice structure and are blocked, slowed down or reflected thereby. In either instance, improper alignment can lead to undesired degrees of channeling (e.g., too little or too much). Additionally, the deviations from the nominal lattice orientation and the dimensions of features formed upon the wafer can affect shadowing, and adversely impact the implantation process and resulting semiconductor devices.
Accordingly, wafers generally possess some indicia of their lattice structure. For example, the wafers are usually designated with Miller Index data, such as 1,0,0, which is indicative of a nominal lattice structure of the wafer relative to the mechanical or cut surface of the wafer. The wafers also typically have a feature that denotes the axis of the wafer crystal. This feature is often a notch or a flat edge along the outer perimeter of the wafer. The number of features and orientation relative to each other are used to denote the crystal type of the wafer and are controlled by Semiconductor Equipment and Materials International (SEMI) specifications. Larger wafer sizes (e.g., 200 and 300 mm) have generally standardized on a notch rather than a flat edge.
A number of commercial aligners are available and generally operate by placing a wafer on the aligner by a robot. The wafer is captured by some mechanism that allows the wafer to spin. This spinning is used to pass the perimeter of the wafer through some type of sensor to locate the notch. A traditional method of capturing the wafer is to use a vacuum chuck located at the center of wafer. However, since most systems operate in a vacuum, it can be difficult to also capture the wafer via vacuum. Additionally, backside contamination can become problematic as one or more wafers may have to pass through the same or different tools multiple times during the fabrication process. This may require multiple re-alignments whereby contaminants such as particles may get transferred to the aligner and the backsides of the wafers. Such contaminants can adversely affect subsequent processing and ultimately degrade device performance.
Accordingly, edge grip aligners are also being used. Edge grip aligners have the advantage of low backside contamination, but have the disadvantage of interfering with the edge of the wafer that is being scanned. In some cases, locating the notch requires re-clamping at a different location and therefore reducing throughput. Once the notch is located, the wafer is generally rotated again to a pre-determined orientation relative to the notch. Typically this orientation is a value that is communicated to the aligner and it may vary batch to batch depending on process conditions.
Conventional aligners may also provide a centering capability. For example, a centering ring can be actuated to mechanically center the wafer after the wafer has been placed on the aligner by the robot. Other aligners can locate the center of the wafer during the alignment process and provide the true center position. Regardless, after the notch has been located and the wafer center has been found, the same or a different robot can retrieve the wafer (e.g., by picking the wafer at a new location that is the wafer center) and maneuver it to a fabrication tool.
Nevertheless, the potential for wafer damage and backside contamination, the difficulty in holding and maneuvering the wafers, and long cycle times associated with centering the wafers, locating the notches and re-orienting the wafers leaves room for improvement in alignment systems.